Semiconductor devices are increasingly becoming more complex with many integrated functions on a single die or chip. As a result, the semiconductor dice have increased in size due to the large number of bonding pads placed on the dice. These bonding pads include signal pads as well as power and ground pads. Typically, if a semiconductor die has 300 bonding pads, then one-third of those pads, or 100 pads, are ground pads. All of the bonding pads must be wire bonded to a leadframe having an equal or greater number of leads to accommodate all of the input and outputs pads as well as the ground pads.
A problem with this approach is that the leadframes become more difficult and more expensive to manufacturer for the following reasons. The pitch between leads has to be very small in order not to unduly increase package size. The downside to a fine pitch leadframe having more than 240 leads is that these high lead count leadframe cannot be stamped but rather must be etched, where etching is a more expensive manufacturing method not desirable for high volume demand. Additionally, some of these leadframes are multilayered to provide a ground plane for the devices. Manufacturing of a multilayer leadframe requires additional processing steps which can add cost to the leadframe. Moreover, a leadframe having a large number of leads will be larger than a similarly pitched leadframe having a lower number of leads. Since the industry trend is toward miniaturization where possible, a large size packaged device can pose design problems when board space is limited.
Hence, a need exists for a high lead count semiconductor device that can address the aforementioned challenges facing existing leaded devices.